1. Technical Field
The present invention relates, generally, to semiconductor manufacturing processes and, more particularly, to the packaging of semiconductor chips using a wire bonded MCM substrate where a top metal layer is designed to minimize inductance and noise contribution.
2. Background Art and Technical Problems
In recent years, noise has become more of a problem in the packaging of semiconductor chips used in high speed digital applications and in radio frequency ("RF") applications. As used herein, radio frequency applications include any applications involving a signal frequency of 500 KHZ or higher. When a semiconductor chip is packaged in a substrate based design, wires are typically bonded to the chip to provide electrical connection to the semiconductor structures formed thereon, including power supply connections and ground connections. The inductance of the ground loop, which includes the current path from the power supply connections through the chip and to the ground connections, has become a limiting factor in many substrate based semiconductor packaging designs. Manifesting itself as a negative contribution to noise performance, the power and ground inductance contributes to simultaneous switching noise ("SSN") in high speed digital applications, and may significantly reduce gain in an RF application.
In an RF application, one hundred picohenrys of ground loop inductance may reduce gain by 1/2 dB. A 3 dB reduction in gain means that the power is cut in half. Thus, a small amount of inductance can result in significant reductions in gain. In addition, the noise figure is adversely affected by such inductance. This is particularly true in narrow band RF applications, but generally applies to all RF applications.
In high speed digital applications, simultaneous switching noise is equal to nL.sup.di /.sub.dt, where "n" is the number of simultaneous switching buffers, "L" is the inductance, and ".sup.di /.sub.dt " is the rate of switching. As faster and faster rates of switching are achieved, the simultaneous switching noise tends to be dominated by the number of simultaneous switching buffers and the inductance. In the past, the number of simultaneous switching buffers was reduced by increasing the number of power and ground pads. Improved manufacturing processes that allow more and more semiconductor structures to be formed on a given size of chip have resulted in designs that are pad limited in many cases. Thus, increasing the number of power and ground pads is no longer an option in many cases.
In the past, efforts to reduce inductance have involved attempts to add power and ground plane to the substrate. In some cases this seemed to reduce total inductance, but the inductances of the top and bottom layer were unaffected, and the desired reduction in noise was not achieved. Other efforts have included adding more power and ground pins to the chip to compensate for inductance in the substrate. But this increases the size and cost of the chip, and sometimes means that a larger and more costly substrate must be used as well. Additional efforts have included attempts to add more power and ground solder pads to the bottom layer of a substrate. While this may reduce the inductance of the bottom layer, it does not affect the inductance of the top layer.
Past efforts to reduce inductance have included attempts to increase the metal thickness on all layers. This is particularly ineffective at high frequency applications, because at high frequencies current essentially flows on the surface of the metal, and the thickness of the metal is virtually irrelevant. Other efforts have included the use of two rings, one for power and the other for ground for wire bond pads, and putting associated vias in the rings. Since vias of the laminate substrates usually cannot be bonded, this limits the positions on the ring that can be bonded causing bond crosses between adjacent pins that lowers the yield of the assembly.
While parasitic inductance has long been recognized as a problem in substrate based semiconductor packages, efforts in the past to reduce inductance have not been altogether satisfactory. There is a significant need for an improved packaging design that reduces the ground loop inductance of a substrate based semiconductor chip package. An optimized power and ground system is needed to permit chip designers to take advantage of substrate based packaging.